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5962-0623601QPC, 5962-0623602QPC
Data Sheet March 28, 2007 FN6473.0
670MHz Low Noise Amplifiers
The 5962-0623601QPC and 5962-0623602QPC are fully DSCC SMD compliant parts and the SMD data sheets are available on the DSCC website (http://www.dscc.dla.mil/ programs/specfind/default.asp). The 5962-0623601QPC is electrically equivalent to the EL5132 and the 5962-0623602QPC is electrically equivalent to the EL5133, reference these data sheets for additional information. These amplifiers are ultra-low voltage noise, high speed, low power consumption voltage feedback amplifiers. Both amplifiers are stable at gains as low as 10. Not only do these devices find perfect application in high gain applications, they maintain their performance down to lower gain settings. These amplifiers are available in SBDIP packages. All parts are specified for operation over the -55C to +125C temperature range.
Features
* 670MHz -3dB bandwidth * Ultra low noise 0.9nV/Hz * 1000V/s slew rate * Low supply current = 16mA * Single supplies from 5V to 12V * Dual supplies from 2.5V to 6V * Fast disable on the 5962-0623601QPC
Applications
* Pre-amplifier * Receiver * Filter * IF and baseband amplifier * ADC drivers
Ordering Information
PART NUMBER
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PART MARKING TEMP (C) PACKAGE
PKG. DWG. #
* DAC buffers * Instrumentation * Communications devices.
5962-0623601QPC 5962-0623 601QPC 5962-0623602QPC 5962-0623 602QPC
-55 to +125 8 Ld SBDIP D8.3
Pinouts
-55 to +125 8 Ld SBDIP D8.3 5962-0623601QPC (8 LD SBDIP) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 CE 7 VS+ 6 OUT 5 NC
5962-0623602QPC (8 LD SBDIP) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 NC 7 VS+ 6 OUT 5 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
5962-0623601QPC, 5962-0623602QPC
Absolute Maximum Ratings (TA = +25C)
Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . Slewrate between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . . . . IIN-, IIN+, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V 1V/s 5mA 20mA
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . .-55C to +125C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192mW
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER RIN CIN BW BW GBWP PM SR tR, tF OS tS dG
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VS+ = +5V, VS- = -5V, RL = 500, RF = 10k, RG = 100, TA = +25C, unless otherwise specified. CONDITIONS Common mode MIN TYP 5 2 RF = 225, AV = +10, RL = 1k RF = 225, AV = +10, RL = 1k 670 90 3000 RL = 1k, CL = 6pF RL = 100, VOUT = 2.5V 0.1VSTEP 0.1VSTEP 55 1000 2.0 10 6.6 RF = 1k, RLOAD = 150 RF = 1k, RLOAD = 150 f = 10kHz f = 10kHz 0.01 0.01 0.9 3.5 MAX UNIT M pF MHz MHz MHz V/s ns % ns % nV/Hz pA/Hz
DESCRIPTION Input Resistance Input Capacitance -3dB Bandwidth 0.1dB Bandwidth Gain Bandwidth Product Phase Margin Slew Rate Rise Time, Fall Time Overshoot 0.01% Settling Time Differential Gain Differential Phase Input Noise Voltage Input Noise Current
dP eN iN
ENABLE (5962-0623601QPC Only) tEN tDIS Enable Time Disable Time 220 175 nS nS
Pin Descriptions
PART 5962-0623601QPC 1, 5 2 3 4 6 7 8 5962-0623602QPC 1, 5, 8 2 3 4 6 7 PIN NAME NC ININ+ VSOUT VS+ CE Not connected Inverting input Non-inverting input Negative power supply Amplifier output Positive power supply Enable and disable input FUNCTION
2
FN6473.0 March 28, 2007
5962-0623601QPC, 5962-0623602QPC Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS b1 M (b) SECTION A-A (c) LEAD FINISH
D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)
8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 D E e eA eA/2 L Q S1 S2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94
E
eA e eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.
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aaa bbb ccc M N
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 3
FN6473.0 March 28, 2007

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